1. Field of the Invention
The present invention relates to a charge pump for a memory device, and more particularly relates to a charge pump for a nonvolatile memory with read voltage regulation in the presence of address skew and to a memory device comprising such a charge pump.
2. Description of the Related Art
As is known, the most recent research in nonvolatile memories, in particular EPROM and FLASH memories, is aimed, on the one hand, at achieving increasingly higher data-storage capacities, and, on the other, at producing memories that are able to operate at low supply voltages to meet the ever-increasing demand for lower consumption typical of portable devices, such as cellphones, digital photocameras, MP3 readers, smart cards, etc., or of consumer electronics.
It is therefore necessary to supply, to the gate terminals of the memory cells, read voltages that are typically higher than the single supply voltage supplied from outside to the memory in order to guarantee a correct reading of the memory cells in any situation.
The read voltages are currently obtained by means of charge pumps having the purpose of boosting the single supply voltage supplied from outside to the memory by an amount such as to reach the read voltage necessary for supplying a sufficient read current to the memory cells.
By way of example, FIG. 1 shows the circuit diagram of a nonvolatile memory using a charge pump according to the prior art. In particular, in FIG. 1 only the parts of the nonvolatile memory that are useful for understanding the present invention are shown.
As illustrated in FIG. 1, the nonvolatile memory, designated as a whole by 1, comprises a row predecoder stage 2 receiving, via an input buffer 4, the addresses ADD supplied to the memory 1, and a row decoder stage 6 cascade-connected to the row predecoder stage 2 and having a plurality of outputs connected to respective word lines 8 of a memory array 10, and on which respective biasing voltages for the word lines 8 are supplied.
The nonvolatile memory 1 further comprises a charge pump 12 having a supply input connected to a supply line 14 set at a supply voltage VCC (typically 2.7-3.8 V) supplied from outside to the memory 1, and an output supplying a read voltage VREAD higher than the supply voltage VCC, which is then supplied to an input of the row decoder stage 6, which uses it for biasing the word lines 8 during the step of reading of the data stored in the memory array 10.
The charge pump 12 comprises a voltage boosting circuit 16 receiving on an input the supply voltage VCC and supplying on an output the read voltage VREAD, and is formed by a plurality of booster stages 18 cascaded together between the input and the output of the charge pump 12.
In particular, the booster stages 18 are of the so-called Dickson type, and are implemented by means of a MOS transistor-boosting capacitor pair and a MOS transistor-pumping capacitor pair appropriately connected together.
Charge transfer from one boosting stage 18 to the next towards the output is via commands from mutually complementary logic-type phase signals, in the example illustrated in FIG. 1 four phase signals designated by A, B, C, D, which are supplied to inputs of the booster stages 18 and are generated by a phase generating circuit 20, which is a logic circuit of a generally known type, and comprises a clock generator stage 22 basically formed by an oscillator supplying on an output a clock signal CK having a pre-set frequency, and a non-overlapping signal generator stage 24 receiving on an input the clock signal CK supplied by the clock generator stage 22, and supplying on outputs the phase signals A, B, C, D, which are then supplied to the booster stages 8.
Finally, the charge pump 12 comprises a regulator circuit 26 receiving on inputs the read voltage VREAD and a reference voltage VREF0, and supplying on an output a logic-type regulation signal STOP assuming a first logic level, for example a high level, when the read voltage VREAD is higher than or equal to the reference voltage VREF0, and a second logic level, low in the example considered, when the read voltage VREAD is smaller than the reference voltage VREF0.
The regulation signal STOP is then supplied to an input of the non-overlapping signal generator stage 24 to interrupt supply of the phase signals A, B, C, D to the booster stages 8 when the read voltage VREAD exceeds the reference voltage VREF0, in order to prevent malfunctioning of the memory 1, such as phenomena of soft-programming or soft-erasing of the memory cells caused by too high read voltages.
FIG. 2 shows the voltage-current characteristic of the charge pump 12 of FIG. 1. As may be noted, the charge pump 12 is able to supply read voltages VREAD having a value that is substantially constant and is equal to the reference voltage VREF0 (Approximately 4.5-5 V) for supplied currents of between zero and a value I0 of the order of mA, and for currents higher than I0, values decreasing down to a value equal to that of the supply voltage VCC when the current supplied by the charge pump 12 assumes its maximum value IMAX0.
It is moreover known that one of the specifications of nonvolatile memories is that they must guarantee the user correct reading of the data as long as the time elapsing between the supply of two successive addresses to the input of the memory is longer than, or at the most equal to, the memory access time, i.e., in other words, as long as the address transition frequency at the input of the memory is lower than, or at the most equal to, the inverse of the memory access time, which, as is known, is defined as the time elapsing between the instant at which an address is supplied in a stable way to the input of the memory and the instant at which the content of the said address is available on the output of the memory.
Consequently, to guarantee compliance with the specifications regarding reading times, charge pumps are sized in such a way as to be able to meet the maximum current requirement by the decoding circuitry to which they are connected as long as the addresses vary at a frequency lower than, or at the most equal to, the inverse of the memory access time, in such a way as to guarantee that the read voltage VREAD will remain constant at the aforesaid value VREF0 over the entire memory operation range.
In particular, the current required from the charge pump by the decoding circuitry is not constant but is proportional to the frequency at which the addresses at the input of the memory vary, and presents a pulse pattern with peaks in correspondence of the transitions of the addresses and a mean value that may be expressed by the following relation: Ixe2x88x9dfADD CDECxc2x7VREAD, namely, a mean value that is a function of the address transition frequency fADD, of the read voltage VREAD, and of the overall capacitance CDEC xe2x80x9cseenxe2x80x9d by the row decoder. It assumes its maximum value when the row decoder xe2x80x9cseesxe2x80x9d the maximum capacitance.
The maximum voltage VMAX that the pump charge can theoretically supply when the current requirement is zero is VMAX=(n+1)xc2x7VCC greater than VREF0, where n is the number of booster stages forming the charge pump, whereas the maximum current IMAX0 that may be supplied by the charge pump when its output voltage is equal to the supply voltage VCC can, instead, be expressed by the following relation: IMAX0=fCKxc2x7CPxc2x7VCC. Namely, it is equal to the product of the supply voltage VCC, the charge pump capacitance CP, and the frequency fCK of the clock signal supplied to the non-overlapping signal generator which generates the phases supplied to the booster stages.
The frequency of the clock signal CK, starting from which the phases of a charge pump are generated, is thus determined in the memory design phase, according, among other things, to the number of booster stages forming the charge pump and the charge pump capacitance CP, in such a way as to guarantee that the read voltage VREAD will remain constant at the value VREF0 referred to above over the entire memory operation range, i.e., as long as the addresses vary with a frequency lower than, or at the most equal to, the inverse of the memory access time, and hence also when the decoding circuitry absorbs the maximum current.
Most flash nonvolatile memories currently available on the market have a memory access time of approximately 100 ns, and hence a maximum allowable address transition frequency of 10 MHz, and the clock signal from which the phases of the charge pump are generated has a frequency such as to guarantee, with a fair margin, that the read voltage VREAD will remain constant at the value VREF0 referred to above over the entire memory operation range.
A sizing for guaranteeing correct reading of data over the entire operation range of a flash nonvolatile memory is, however, in contrast with the recent increasing market demand for so-called xe2x80x9cstackedxe2x80x9d memory devices, i.e., memory devices in which flash nonvolatile memories are used in combination with faster memories, such as SRAM memories, that is, volatile memories having much shorter access times than flash nonvolatile memories.
In particular, in a stacked memory device, a flash nonvolatile memory and a faster volatile memory are substantially connected in parallel, i.e., they share, either in part or completely, the same addresses and have their outputs connected in parallel together. Selection of either memory may be made at input via a so-called chip enable signal supplied to the input buffers of the memory, or else at output via a so-called output enable signal supplied to the output buffers of the memory.
In this type of memory devices, when the two memories share the so-called chip enable signal, often a phenomenon commonly referred to as the address skew phenomenon occurs; i.e., it often happens that the address transition frequency at the input of the flash nonvolatile memory exceeds, even abundantly, the maximum frequency acceptable for flash nonvolatile memories (a value of even 66 MHz may be reached), and this phenomenon is the cause of degradation of the performance of the memory device in particular conditions of use thereof.
In particular, the address skew phenomenon is particularly dangerous when it is intended to carry out first a set of readings of the data stored in the faster volatile memory and then to access the data stored in the flash nonvolatile memory. In fact, during the step of reading of the data stored in the faster volatile memory, in which address transition occurs at much higher frequencies than the maximum frequency acceptable for flash nonvolatile memories, it is possible, given the higher demand for current by the decoding circuitry, that the read voltage supplied by the charge pump of the flash nonvolatile memory will drop below a limit value, usually referred to as xe2x80x9cfailure voltagexe2x80x9d, below which the number of readings aborted is such as to lead to failure when an attempt is made to actually access data stored in the flash nonvolatile memory.
FIG. 3 illustrates the decay of the read voltage VREAD in a flash nonvolatile memory according to the prior art in the presence of address skew. In particular, in FIG. 3 the bold line indicates the graph as a function of time of the read voltage VREAD in the presence of addresses having a transition period of 15 ns and in the case where the clock signal CK supplied to the phase generator stage has a period of 60 ns, whilst the thin line indicates the failure voltage VFAIL.
The disclosed embodiments of the present invention provide a charge pump for a memory device that overcomes the above described drawbacks.
In accordance with one embodiment of the invention, a charge pump for a memory device is provided. The charge pump includes a clock generator supplying an output clock signal; a phase generator receiving the output clock signal and supplying phase signals; a voltage boosting circuit receiving a supply voltage and the phase signals and supplying a read voltage higher than the supply voltage; the clock generator including a comparator circuit having a first input receiving the read voltage, a second input receiving a reference voltage, and an output supplying a selection signal indicating the outcome of the comparison between the read voltage and the reference voltage; and a selection circuit have a first signal input receiving a first input clock signal, a second signal input receiving a second input clock signal having a frequency higher than the frequency of the first input clock signal, a selection input receiving the selection signal, and an output supplying the output clock signal and operatively connected to one of the first and second signal inputs in response to the selection signal.
In accordance with another embodiment of the invention, a memory device is provided that includes the charge pump as recited above.